Dow Corning and imec to Develop Technologies for 3-D IC Semiconductor Packaging
July 10, 2013
Technology enables room-temperature bonding and debonding processes based on standard manufacturing methods.
Dow Corning said July 8 it has joined nano-electronics research center imec to develop 3-D integrated circuit (IC) packaging technologies.
By integrating multiple chips into a single package, 3-D IC technology may reduce form factor and power consumption and increase bandwidth to enable more efficient inter-chip communication for next-generation microelectronics devices. But before 3-D IC fabrication can see broader adoption, it will require innovative advances in materials and processing technologies.
One of the key challenges imec is tackling is the bonding of the device wafer to a carrier wafer prior to wafer thinning and the safe debonding of the thin wafer after completion of backside processing. This was Dow Corning’s goal when designing its temporary bonding solution, which was aimed at simple processing using a bi-layer concept comprising an adhesive and release layer. The Dow Corning technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods.
Dow Corning and imec will explore its temporary bonding CMOS-compatible solution for 3-D Through-Silicon-Via semiconductor packaging. The collaboration will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing processes.
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